The invention relates to a semiconductor memory device, and more particularly, to a reduction in the power dissipation in a self-refresh operation of a dynamic random access memory (DRAM).
A DRAM used in a portable unit such as a personal computer receives power from a storage battery of the portable unit to perform a self-refresh operation to maintain data which has been written to it. Accordingly, the battery dissipates power to maintain the stored data even when the portable unit is not operating. To preserve power enhance the operable time interval of the portable unit, the power dissipation for the self-refresh operation of the DRAM must be reduced.
FIG. 1 is a schematic block diagram of a conventional DRAM 11.
The DRAM 11 includes a plurality of cell blocks, four are shown here, BLK0-BLK3. Each of the cell blocks BLK0-BLK3 comprises a memory cell array 12, a row decoder 13, an equalizer 14, a sense amplifier bank 15 and a column decoder 16. Only the cell block BLK0 is shown in detail in FIG. 1.
The memory cell array 12 comprises a plurality of bit line pairs BL0, /BL0 to BLm, /BLm, a plurality of word lines WL0 to WLn, and a plurality of memory cells C (see FIG. 2). Each memory cell C comprises a single transistor and a single capacitor which are connected to an associated intersection of the bit line pairs BL0, /BL0 and the word lines WL0 to Wln.
The row decoder 13 receives an external address EXAdd provided via a switch 17 as an address signal Add and activates one of the word lines WL. Assume now that a word line WLi is activated by the row decoder 13 as shown in FIG. 2. The column decoder 16 responds to a column address which is externally supplied to turn on a data bus switch 18 to connect the bit line pair BLi, /BLi to a data bus pair DBi, /DBi. Information stored in the memory cell C is read from the bit line BLi, amplified by the sense amp 15, and delivered externally on the data bus pair DBi, /DBi.
A refresh operation will now be described. A row control circuit 21 receives a row control signal /RAS and a column control signal /CAS, enters a CBR refresh mode when "CAS before RAS" or CBR condition is detected, which means that the falling edge of the column control signal CAS occurs earlier than that of the row control signal /RAS as shown in FIG. 3, and delivers a control signal M1 to the switch 17 for controlling the CBR refresh operation.
In this mode, the row control circuit 21 delivers a refresh clock signal RCLK to a refresh address counter 22, which counts the clock signal RCLK to generate a refresh address signal IAdd, which is then applied to the switch 17. In response to the control signal M1, the switch 17 passes the refresh address signal IAdd from the counter 22 to the row decoder 13 of the respective cell block BLK0-BLK3. The row decoder 13 of the cell block BLK0 activates the initial word line WL0 in response to the refresh address signal IAdd. The memory cell C connected to the activated word line WL0 is then refreshed.
Specifically, referring to FIG. 2, the sense amp 15 of the cell block BLK0 is activated by an H level power supply PSA and an L level power supply NSA, and when activated, amplifies a signal read from the bit line. The memory cell C connected to the activated word line WL0 is refreshed in this manner.
When the memory cell C is refreshed, a reset operation takes place automatically, thus precharging the bit line.
Specifically, the row control circuit 21 delivers an equalize signal EQ of an H level to the equalizer circuit 14, which is supplied with a precharge signal PR of a given potential (which may be equal to one-half Vdd, for example) from a bit line precharge circuit 23, where Vdd is a power supply used to operate various circuits.
As shown in FIG. 2, the equalizer circuit 14 comprises a pair of N-channel MOS transistors connected between the bit line pair BLi, /BLi, with the equalize signal EQ being applied to the gates of the transistors and the precharge signal PR being applied to the node between the transistors. In response to the equalize signal EQ of the H level, the equalizer circuit 14 precharges the bit line pair BLi, /BLi to the potential of the precharge signal PR (which is one-half Vdd).
A self-refresh mode is entered after a given time interval has passed from when the memory cell C connected to the initial word line WL0 of the cell block BLK0 is refreshed in the CBR refresh mode. In the self-refresh operation, a memory cell C connected to a word line located next to the word line having the refreshed memory cell connected to it (i.e., the second word line WL1 of the cell block BLK0) is similarly refreshed. When a memory cell C connected to the last word line Wln of the cell block BLK0 has been refreshed, the refresh operation for all the memory cells C in the cell block BLK0 is completed.
Subsequently, the word lines of the cell block BLK1 are successively activated to refresh the connected memory cells. In a similar manner, the memory cells C in the cell blocks BLK2 and BLK3 are refreshed. When the refresh operation for the memory cell C connected to the last word line of the cell block BLK3 is completed, the count value of the refresh address counter shown in FIG. 1 is reset, returning to the initial refresh address or delivering the refresh address signal IAdd for the word line WL0 of the cell block BLK0.
Salvaging of a defect in the memory cell C will now be described. As shown in FIG. 1, the DRAM 11 also comprises a redundancy decision circuit 24, and the memory cell array 12 includes a redundant word line RWL, which is connected to a redundant word line drive circuit 25 in the row decoder 13.
An address of a defective cell which was previously detected by a test, is stored within the redundancy decision circuit 24, which determines whether the address Add from the switch 17 coincides with the stored defective address and delivers a redundancy control signal ROM to the row decoder 13. By way of example, assume that the circuit 24 delivers a redundancy control signal ROM having an H level for the coincidence between the defective address and the address Add. In response to the high redundancy control signal ROM, the row decoder 13 does not activate a word line which was chosen in accordance with the address Add. The redundant word line drive circuit 25 activates the redundant word line RWL in response to the redundancy control signal ROM. As a consequence, a read/write access as well as a refresh operation take place with respect to a memory cell C connected to the redundant word line RWL rather than with respect to the memory cell C connected to the word line at the defective address.
The current consumed during the refresh operation (or refresh current) comprises a DC current component representing a steady-state consumption and an AC current component representing a consumption during the memory cell refresh operation. The DC component represents the consumption by the bit line precharge circuit 23 and the refresh address counter 22, while the AC component represents the current required for driving the word line WLi and an operating current of the sense amp 15.
However, it should be noted that if a defective location is replaced by a redundant memory cell which allows a normal read/write operation through an address conversion, this does not physically remove the current consumed by the defective location. That is, there is a current flow through the defective location, which increases the DC component.
As shown in FIG. 5, suppose that there is an electrical short circuit across a word line WL and a bit line BL. The sense amp 15 connected to the bit line BL is supplied with the precharge signal PR from the bit line precharge circuit 23, whereby the bit line BL is precharged to one-half Vdd. On the other hand, the word line WL is connected to a word line drive circuit 26 and is set to a low potential (a ground potential), when it is not activated. Thus, there occurs a steady-state leak current from the bit line BL to the word line WL, as indicated by an arrow.
Defective locations usually occur in a random manner, and the number of such locations increases with an increase in the integration level of memory cells and the sophistication of the fabrication process. As a consequence, the power dissipation during the self-refresh operation increases by an amount corresponding to the steady-state current flow through the defective location or locations, thus increasing power consumption.
Japanese Unexamined Patent Application No.5-128858 discloses a method for reducing a current flow through a defective location. In the method, the bit line is precharged at one-half Vdd level immediately before the read operation and is maintained at the ground potential except for during the read operation, to reduce a defective current. However, the method requires placing all the bit lines at the ground potential when the refresh operation takes place for all the word lines of the memory cell array inclusive of both non-defective and defective locations. This means that the precharge-ground potential (discharge) process takes place even for the refresh operation for a defect-free normal address, and this wasteful operation increases the AC current component, leading to an increase in the power dissipation. In addition, the disposition of a circuit which establishes a ground potential on the bit line pairs and a ground potential line connected to the circuit within the memory array increases the chip area.
Japanese Unexamined Patent Application No. 8-203268 discloses another method which eliminates a leak current path caused by a cross-line defect between a word line and a bit line by maintaining the bit line in a floating state when the memory cell is not accessed. By setting the bit line in a floating state, any charge which remains on the bit line is restored to the precharged level, so that an increase in the AC current component is prevented when a control is exercised uniformly for all addresses, irrespective of whether they are non-defective or defective.
However, the second method is not practicable. In a DRAM in particular, a charge of a minimal quantity stored in a capacitor which is made as small as possible is applied to a bit line as information for a memory cell, and a minimal amplitude on the bit line is differentially amplified. Accordingly, if the bit line is floating, noise generated in the substrate or opposing electrodes of a memory cell having increased capacitances may cause the bit line to have an unexpected value due to an electrostatic coupling, and in worst cases, may change the content stored in the cell storage capacitor and thus destroy the information.
It may be contemplated, as modifications of the above method, that only a defective bit line be controlled from its precharge level to the ground level or be made floating. However, this requires the provision of a wiring for all of the bit lines which supply a control signal or of fuses to allow disconnection, and thus requiring a substantial increase in the chip area.